The present invention relates to a memory system and, more particularly, to a memory system capable of restraining a reduction in a receiving margin at a signal receiving side even at high frequencies.
As well known, in a DRAM system, signal transmission carried out on a bus between a memory controller and each DRAM inevitably incurs delays attributable to influences on a bus, a substrate, and the like, such as wiring capacitor, parasitic capacitor.
Recently, as the data rate of a DRAM is becoming higher and higher, a proportion of the signal propagation delay in the operation cycle is increasing. To cope with this trend, a proposal has been made about restraining that reduction of a signal receiving margin which is caused by the propagation delay. For example, the cycle time of a system operated at a clock of 400 MHz is 2.5 ns, while the propagation delay of a DQ signal between memory controller DRAMs reaches 1.6 ns.
Practically, DRAM systems have been known which transmit and receive data at both leading and trailing edges of a clock signal. In this case, a cycle time of one bit is virtually as short as 1.25 ns, which makes it impossible to match or adjust bi-directional data between a DRAM and a memory controller by using only a unidirectional clock signal.
Hence, there has been proposed a memory system which separately has a write clock and a read clock. In this memory system, data timing is adjusted or matched to the write clock in writing data from the memory controller to the DRAM. On the other hand, the data timing is matched to the read clock in reading data out of the DRAM to the memory controller, as shown in FIG. 22 (will be hereinafter referred to as “related technology 1”).
As mentioned above, the memory system according to the related technology 1 requires two phases of clock signals for readout and write-in operation.
The configuration of a DQ in this related technology 1 is equivalent to the bit configuration of a discrete DRAM, and has a bit width of 4/8/16, etc. It is expected in the future that there will be a demand for a further higher data transfer speed. To meet such a demand, a further expanded bit width will be required.
FIG. 23 shows a memory system in which the DQ bit width in the related technology 1 has been expanded (hereinafter referred to as “related technology 2”). The related technology 2 relates to a memory system equipped with a plurality of memory modules on which a plurality of memory devices are mounted. In this related technology 2, however, the number of write clocks and read clocks must be increased as the number of parallel DRAMs. This memory system has a shortcoming in that the number of clock lines of the entire system increases with consequent higher cost of the system.
There is another problem in that the timing margin on a receiving side reduces due to a difference between a DQ signal and a clock signal in signal propagation time attributable to a wiring layout, signal drivability, the difference in electrical termination method, etc. in a system.